1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system and method for testing an integrated circuit device with asynchronous clocks or dissimilar design methodologies.
2. Description of Related Art
When a microprocessor or system-on-a-chip (SoC) is designed, it is important that the resulting chip design be tested to ensure proper functioning. In order to test a microprocessor or SoC chip, typically, the chip is designed to include built-in scan chains for scanning in test patterns to individually test the cores and other circuitry elements of the microprocessor or SoC. A scan chain is formed by connecting a set of sequential elements, such as flip-flops or shift register latches, as a shift register chain in a processor or SoC design. Most modern processor or SoC chips have multiple scan chains to reduce testing application time and testing cost.
Highly integrated microprocessor and SoC designs contain many different functional elements. Some of these functional chip elements may be asynchronously clocked, i.e. clocked using a different clock speed than a common clock for the processor or SoC, or developed with different design methodologies. For example, in modern designs, the core logic of microprocessors run with gigahertz clocks. However, when input/output (I/O) and memory devices are incorporated on the same chip, these devices will require different clocking requirements. An example of a microprocessor or SoC design that includes asynchronous clock boundaries may be a 4 GHz processor that communicates with a 300 MHz input/output interface.
Similar asynchronous clock boundaries arise when different design methodologies are used in the same microprocessor or SoC. An example of chip elements designed using different methodologies may be a Generalized Scan Design (GSD) element that connects to a Level Sensitive Scan Design (LSSD) element. For example, GSD uses an edge triggered latch design with a single clock. LSSD uses a transparent latch design with a system clock and a B clock. Thus, during testing, only one clock is needed for GSD, yet two clocks are needed for LSSD. Moreover, since GSD uses edge triggered latches versus the transparent latches that are used in LSSD, the setup and hold times for these design methodologies are different. All of this gives rise to different clock boundaries conditions being present in the microprocessor or SoC design.
For a scan based designs, i.e. designs in which data is scanned through all of the latch elements in the scan chains of the various functional elements of the microprocessor or SoC, the different clocking requirements create asynchronous boundaries between the core logic and the other functional elements. Scanning across asynchronous clock boundaries is problematic because latch setup and hold times cannot be established reliably between the two clocking environments.
This is especially a problem when testing the operation of the microprocessor or SoC. During testing operations, the desire is to have all digital logic running on the same clock. This will allow the testing equipment to scan all latch elements to initialize the chip to a known state. This, however, is not possible with microprocessors or systems-on-a chip designs that have different clocking domains on the chip. As a result, during testing, the test equipment must treat each clock domain separately.
For scan based designs, one approach to addressing this issue is to design the clock distribution network such that both the native clock, i.e. the clock upon which a chip element operates, and a high speed common clock, also referred to as the system clock, are provided to the logic for asynchronous clock domains. Logic to implement a multiplexing scheme for the selection of clocking signals is provided on the chip to allow switching between the two clock domains. The high speed clock is used during scan operations to eliminate hazards when scanning across the asynchronous boundary. The native clock is used in a functional mode when the chip is operating.
This approach requires that all logic be timed at the fastest clock speed. For example, if the chip had 2 GHz and 300 MHz chip elements, the 300 MHz elements would need to be timed as 2 GHz elements to meet test requirements. Since they only need to run at 300 MHz functionally, this is not a very efficient design from a circuit area and power standpoint.